A conventional NPN transistor 10 is illustrated in FIG. 1 wherein a P- substrate 12 has a N+ buried region 14 disposed thereon. A N- epitaxial layer 16 is deposited on the N+ buried region 14. A pair of N+ regions 18, 20 reach through the N- layer 16 and provide access for a contact 22 to define a collector electrode which is accessible via line 24. A P region 30 is defined in the N- layer and contacts 32, 34 provide access to this base region. A line 36 provides access to contacts 32, 34. A N++ region 38 is provided in the P region 30 and a contact 40 and a line 42 define the emitter of the transistor 10. The base region 30 may be diffused or ion implanted. A SiO.sub.2 layer 21 provides isolation.
In the prior art pertaining to this and other bipolar transistor designs, the sheet resistance value of the base is a compromise of conflicting demands. For a given emitter and base width, a high base sheet resistance is desirable to achieve a high performance device by increasing the gain, increasing the emitter injection efficiency, lowering the emitter base capacitance, and increasing the frequency response of the transistor.
A high base sheet resistance, however, will result in high extrinsic base resistance which is undesirable for certain circuit applications.
Another serious consequence of the high extrinsic base resistance is increased transistor noise. Increased noise is undesirable in most applications, but it is especially critical in applications where detection and processing of low level signals is required. A low base sheet resistance is therefore desirable to achieve low extrinsic base resistance and low noise.
Prior art transistor base sheet resistance values have been compromised between these conflicting demands for high and low sheet resistance. A bipolar transistor which resolves this conflict and provides for high gain, low extrinsic base resistance, and low noise while not significantly increasing the manufacturing costs of prior art transistors is therefore highly desirable.